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Contains general information and definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast conducted synchronous transient disturbances.The objective is to describe general conditions to obtain a quantitative measure of immunity of ICs establishing a uniform testing environment. Critical parameters that are expected to influence the test results are described. Deviations from this specification should be explicitly noted in the individual test report. This synchronous transient immunity measurement method uses short impulses with fast rise times of different amplitude, duration and polarity in a conductive mode to the IC. In this method, the applied impulse has to be synchronized with the activity of the IC to make sure that controlled and reproducible conditions can be assured